I am building an EGA adapter using a Gowin Tang Nano 9K FPGA. Everything seemed to work perfectly(first picture), but after about 12 hours of powering up, I noticed that the BRAM text buffer was randomly corrupted(second picture). Could this be bit flip caused by cosmic ray? If so, what can I do to fix this?

I need to design the data interface between FPGA and custom chip.

The chip should be running at high speed (GHz).

Now, FPGA is not able to receive the data at this rate, and there cant be too many pins on the chip.

Is it possible for the chip to write the data via PCIe to FPGA memory with incrementing the address ?
How this would be done ?
Thanks :)

I want to start with FPGAs, for simple chip prototyping and possibly emulation of some old chips(intel 8086 or similiar), is this a good option?

https://www.digikey.com/en/products/detail/altera/EK-10M08E144/4976140

Do i need any other equipment for it?(e. g. external cooling or something), or can I just connect some leds up to it and do something.

Are LE's basically equivalent to the amount of logic gates(AND, OR, etc.) which I can have on 1 fpga?

pwd_incorrect goes high, even though correct unlock bits provided(1011). unlock signal goes high at the end when current_state recieves its last correct bit. I want to know why the pwd_incorrect signal goes high in between. if give serial data (1101), then in the second bit, pwd_incorrect should go high. Can someone explain why its happening. I have attached the waveform figures, SV testbench, SV module.

module & testbench code:

https://github.com/TripleEx3/mealy_fsm_unlocking.git

waveform:

current_state & outputs:

mealy_fsm:

I have recently started learning about transaction level testbenches. My DUT has an AXI-S interface on its port list, and I'm trying to implemented a driver that will drive the pins on the DUT. Here is my code

module driver(
    ref uvm_tlm_fifo #(Input_tran) stim_f,
    output logic [7:0] m_axis_tdata,
    output logic       m_axis_tvalid,
    output logic       m_axis_tlast,
    output logic       bad_frame,
    input logic        m_axis_tready,
    output bit clk, 
    input bit rst
);

    Input_tran t;

    always @(negedge clk) begin

        if (!rst) begin
            if(stim_f.try_get(t)) begin
                // for (int i=0; i<t.payload.size(); i++) begin
                foreach(t.payload[i]) begin
                    m_axis_tdata = t.payload[i];
                    m_axis_tvalid = 1;
                    if(i == t.payload.size() - 1) begin
                        m_axis_tlast = 1;
                        bad_frame = t.bad_frame;
                    end
                    else begin
                        m_axis_tlast = 0;
                        bad_frame = 0;
                    end

                    while (m_axis_tready != 1) @(posedge clk);
                    // do begin
                    //     @(posedge clk);
                    // end while(m_axis_tready != 1);
                end
            end
        end

        else begin
            reset();
        end
    end

    always #10 clk = ~clk;

    task reset();
        m_axis_tdata = 'x;
        m_axis_tvalid = 0;
        m_axis_tlast = 0;
    endtask

endmodule

When I use the do-while loop to check if ready is high, it works as expected. But the drawback is that it will wait for a posedge at least once, so this causes the pins to go out of sync by half a cycle (because of the negedge always block)

So instead, I tried using a while loop, but I observed that the foreach loop loops to the end of the payload and just drives that word on the data bus, almost as if it completely ignored the always block.

Is there a standard approach to implement a handshake in the testbench? I feel like I'm missing something trivial. The same thing happens if I use a wait(ready) in the always block as well.

Hi. I have never used BRAM before.

My project requires reading image pixel data from BRAM in upper module,

and performing calculations with this data in lower module and writing the result to another space in BRAM.

Can I access BRAM through code in an automatic inference way?

Or should I use IP block design in this process?

Can the module read 0, 1 data from 1bit depth image file? Should I convert it to text file?

Please let me know how to specify file and upload it to BRAM.

I appreciate any comments.

Hi,

I am trying to modify my AXI IP core to work in AXI4lite because I notice problems when it is working in AXI4full.

it stops for some reason:

This is my workaround to try and chanfe axi configuration:

However, I got some errors:

Do you know what this is all about?

Why is Riviera not letting me typedef a parameterized interface? Every other example I have works.

typedef myclass#(.BUS_WIDTH(32)) class32_type; // works!
typedef myinterface#(.BUS_WIDTH(32)) my32busIF_type; //parse error: unexpected #

however this works:

typedef virtual myinterface#(.BUS_WIDTH(32)) myVIFbus_type; // works!

Which is the biggest WTF.

I want to declare an input and output bus, and a typedef a virtual interface type based on the same subtype. Without the typedef I have to have the bus defined in three places rather than one which could become mismatched. Having all three be defined/declared from one type would ensure they stay coherent.

Im trying to add 2 HDMI ADV7511 chips on my custom Zynq 7020 FPGA board, there are a lot of references like the Zedboard and others but I don't seem to find any board that has 2 of these chips, does anyone know of any?

The only issue that I can think of is the I2C lines. Since both chips will have the same address, do I need an I2C MUX, or since the IP spawns in the I2C controllers in the PL, I don't?

I'm using xilinx for my project wherein I also want to do FPGA...but the problem is there is no waveform being generated here😭I'm UG student...would someone please guide me...🙏

I’m an American university student trying to buy an FPGA for some side projects and I’m wondering if anybody knows of any student discounts I could take advantage of

Board recs also appreciated

The ButterStick FPGA dev board has a 125MHz clock coming from the KSZ9031 pin 41. I can not establish the pin it is connected to on the ECP5 FPGA. I have looked at the schematic. https://github.com/butterstick-fpga/butterstick-hardware/blob/main/hardware/ButterStick_r1.0/Production/ButterStick-r1.0a-sch.pdf Does any one have pointers to where I can look?

I am experimenting with HX711 sensor (24-bit Analog-to-Digital Converter (ADC) for Weight Scales).

I have created FPGA design on my Digilent ZyboZ7 board and connect 8 HX711 sensors via PMODs and experimented with 50kg load cell sensors (dismounted an old Laica mechanical bathroom scale).

In attached pictures the experimenting FPGA block design can be seen, on second picture is my running HW test setup and on third is my latest PCB with 6x HX711 on PMOD connector.

For experimenting purposes I have added tone generator in FPGA design that outputs to ZyboZ7 SSM2603 audio codec HPH OUT output (headphone output). Instead of headphones I connected 5V dual PC external speaker.

When sensor ADC count is above certain threshold level (e.g. 7500 counts), FPGA will produce tone of some frequency, with decrementing gain and some duration. Each sensor has SW configured different frequency tones (B4=493.88Hz, A4=440.00Hz, G4=392.00Hz, F4=349.23Hz, E4=329.63Hz, D4=293.66Hz, C4=261,63Hz and B3=246.94Hz). On ZyboZ7 in embedded Linux I also wrote a control sw application that serves as control interface between FPGA and data consumers.

Summing it all together it is kind of 8 tone instrument with possibility to display ADC data on PC side.

This all together then allowed me to experiment and see how sensitive sensor is, detect at which finger tapping force it already produce peak of ADC count data over 7500.

I was surprised how sensitive the HX711 and load cell sensor is. Just slightly tapping with finger on load cell gives several thousand peak counts on ADC data. I was using 128 gain input on HX711.

I also wrote a simple python script that runs on Ubuntu PC and captures ADC data sent from ZyboZ7 for all HX711 sensors. Data is sent via UDP Ethernet packets. Python script displays them in some kind of real time plot. Python plotting is not very real time performance friendly. But for up to 8 sensors it display GUI plot in reasonable FPS update rate to track ADC data. On this GUI plots it can be seen in real time the peaks of ADC data when tapping/pressing the load cell.

Here is link to video with audio (https://drive.proton.me/urls/CBXBVY0T3C#rRAIsK5UxnJB) that shows this experimenting. I did not find a way to add directly mp4 video in this post. Probably because it is too big.

Hi, I'm pretty much new to FPGA, and am doing a project for which I want to do timing analysis. I figured out that we need to write some timing constraints in a xdc file basically to set up the clock frequency from the FPGA internal clock and connect it with the clock in my top module. The point where I'm stuck at is to figure out which Pin from my fpga board is the coorrect pin to use as my Clock Instance and connect it. I searched over Internet and went over the fpga datasheet but its too much information without a proper explanation (atleast for me right now). I would really appreciate some tips on how to find IOpin placement strategies. I am using a xcz7045ffg9001 device in vivado

I have looked at many vendors for an equivalent AMD fpga but they are much higher priced then the A3P250. The only one I could find was marked as an obsolete part, so my search continues. If anyone knows of a good AMD alternative, please let me know.

I wanted to implement a parallel processes which utilizes same resources (like memory) but seperate read and write processes. read write must be independent of each other. To avoid multiport error, I used a single always block and wrote both rx and tx fsm in that. Is that a good practice to avoid multiport errors ?

What specific parts and manufacturers were the hardest to find in the market after creating the BOM?

I’m working on an FPGA-based PCIe exerciser, referencing ARM's SBSA-ACS repo. The goal is to build a test card that can act as a PCIe endpoint, handle TLP transactions, DMA, and work in a validation setup.

Looking at:

Xilinx UltraScale+ (e.g., ZCU102) – Decent PCIe support, AXI-based DMA.Intel Stratix 10 – High-performance but expensive.Lattice ECP5 – Cheaper but only PCIe Gen2.

Has anyone worked on something similar? Any better FPGA suggestions or things to watch out for?

Title says it all!! I am so so excited! It has been my goal all through college. I had my 3rd round/onsite interview last week and they just emailed me about the offer. I am going to accept. Its in the defense sector. Really interesting work, mostly FPGA but also some DSP which i love!

Interview was hard! Multiple hours of technical questions and resume review. I didnt get all the questions right and I was so nervous 😞, but it was good enough!!

It will start after graduation in June. Curious about others memories of their first offers? I am just super happy right now and wanted to post!

I'm making game machine by z80 and FPGA. But I don't know good FPGA Board. Do you have recommend FPGABoard? If possible, I’d like the cheaper option.

Hi,

Is it worth it for 170 euros? I want it for my hobby hdl projects. I was looking to buy something Artix7 based (like 200T) but either they don't have pcie or they do but cost 700+ euros.

Zynq ultrascale+ ones are also interesting. Some of them have 4 GB of PS side ddr4 (artix7 ones are ddr3, 512MB) but they are around 450€.

Have you worked with Gowin software? Can you use open source tools to generate bitstream for this device? Or are you locked to a terrible software with tons of bugs?

Hi all, I’m fairly new to the world of FPGA development, coming from a DSP/Programming background. I’ve done smaller fpga projects before, but solo. I’m now starting to collaborate within my team on a zynq project so we’ve been scrutinising the design process to make sure we’re not causing ourselves problems further down the line.

I’ve done my research and I think I understand the pros and cons of the choices you can make within the Vivado design flow pretty well. The one part I just don’t get for long term projects is the using the Block Design for top level connections between modules.

What I’d like to know is, why would an engineer with HDL experience prefer to use block designs for top level modules instead of coding everything in HDL?

I have been developing with the Lattice IceSugar-Nano from MuseLab for quite a few months now and must say it is useful for learning new hardware communication protocols.

So far I have learned the ST7735S TFT LCD Screen, SD Memory 4 bit SD Mode, and UART protocols.

I've been able to develop with it in Ubuntu 22.04 VM environment.

Just thought I'd share a very cheap useful FPGA that has worked for me recently.

I'm supposed to be an FPGA engineer, meaning I mostly want to work with HDL, at least at the beginning of my career. I have a general background in computer architecture and embedded systems, but I want to go all in on digital design.

The problem is that the role of an FPGA engineer seems to be shifting towards SoC engineering, requiring more involvement with the embedded software side, particularly the PS (Processing System) part. This is exactly the kind of work I initially wanted to avoid—anything related to microcontroller configuration.

At least with microcontrollers, modern IDEs do a lot of the dirty work for you through a GUI, where you just select what you need, and everything is configured automatically. But with the PS, it's a nightmare—at least from what I’ve experienced so far.

I recently tried to light up an LED routed to a PS GPIO and ended up manually writing C structures for the required registers, which was a complete nightmare. Later, I learned that there are libraries that abstract this part, but the most frustrating thing is that, somewhere in the documentation, you’ll find out that you need to configure a specific register before configuring the GPIO. If you don’t, good luck debugging.

So, does anyone have good references for the PS part that explicitly list which registers need to be configured to enable a specific PS peripheral?

HI, I have worked with the AXI4 Peripheral IP with a Slave Interface and it was easy to modify the Verilog code. Now I am looking to use the AXI4 Peripheral IP with a Master interface and I don't know where to modify the Verilog files. My goal is to be able to write data to a AXI Data FIFO via the AXI4 Peripheral IP. Reading the FIFO will be from the ARM which is very straight forward. I'm looking for help with the AXI4 Peripheral IP Verilog Files. I thought I could add a data port to the IP and then set the txn port high to write my dat to the FIFO.

Can anyone share how this is done.

Thank you